Nanoscale and near nanoscale devices are important for a wide variety of applications. They include increasingly high density semiconductor integrated circuits and a wide variety of electronic, optical, magnetic, mechanical and biological devices.
The performance of such nanoscale devices typically depends on the shapes and dimensions of their structures, and they are typically designed with precise shapes and dimensions to perform a desired function. They are fabricated by one of a variety of techniques such as lithography, etching, material deposition and imprinting. However, these fabrication techniques are not precise at the nanoscale level. They have intrinsic defects due to the statistical nature of each processes and extrinsic defects due to fabrication environment (such as dust particles). As a consequence, the devices often deviate from the desired design due to geometrical (topological) defects, structural defects or both. Typical geometrical defects include edge roughness, deviation from straight or circular edges, deviation from planarity and sidewalls that are not vertical. Typical structural defects include crystal defects, grain boundaries and material property deterioration. As the size of the devices becomes smaller, these defects increasingly degrade device performance.
FIG. 9, which is useful in understanding problems to which the invention is directed, schematically illustrates a conventional nanoscale device with exaggerated edge roughness, deviation from planarity and deviation from verticality. The nanoscale device 8 typically comprises a macroscale substrate 11 supporting one or more nanostructures 10 which can protrude from the substrate. The nanostructure 10 typically includes an exposed “top” surface 13 distal to the substrate interface and one or more exposed lateral surfaces 14 that extend from the substrate surface to the top surface 13, intersecting the top surface at one or more edges 9. To be considered nanoscale or near nanoscale, the nanostructure 10 should have a minimum feature, such as width W, that is less than about one micrometer and, more commonly, less than about 200 nanometers.
It is usually intended for optimal performance that the exposed distal top surface 13 be smooth and parallel to the substrate. The exposed lateral surfaces 14 should be ideally vertical to the surface 13. They should be substantially free of non-vertical portions 6, and the edges 9 should be smoothly straight or, if curvature is desired, smoothly curved. The edges should be substantially free of rough, irregular features 7. In many applications, the nanostructure ideally has a high aspect ratio as measured by the ratio D/W where W is the minimum lateral dimension and the height D of the sidewall.
One approach to reducing edge roughness is to fabricate the device 8 with a polymeric resist mask that has been heated to the flowing temperature of the resist. This heating and the resulting flowing typically smoothes the edges of the resist. However, the same heating and flowing can round the edges causing them to deviate from verticality and round the surfaces from planarity. To avoid severe deviation of the vertical sidewalls and rounding of the surfaces, the duration of heating to remove edge roughness is typically very short. Consequently only part of the edge roughness is removed. As a result, the resist sidewalls and surfaces are often deformed.
To overcome the degradation of the resist structure sidewalls and surfaces, U.S. Pat. No. 6,905,949 to Artia suggests coating the entire patterned resist structure with a second material whose flowing temperature is higher than the resist and then heating to the thus-coated resist to flowing temperature. The problem with this approach, however, is that the coating encasing the resist at all interfaces makes it difficult for the resist to change shape.
It should also be noted that masking by resist is typically an early step among the many required to form a nanoscale device in a hard, high melting temperature material such as semiconductor, metal or dielectric, or mixture of them. The previous methods that blankly heat entire devices for smoothing a resist feature cannot be applied to the hard, high melting temperature materials, since the heating will melt and destroy the substrate and other surrounding structures. Consequently, even a completely smooth resist mask cannot prevent subsequent processing steps from creating new defects. Accordingly, there is a need for improved methods for repairing and enhancing the structural features of nanoscale devices.